An integrated circuit may be formed on a silicon on insulator (SOI) substrate, which includes a handle wafer of a semiconductor material such as single crystal silicon, a buried oxide layer located on a top surface of the handle wafer, and an SOI film of semiconductor material such as single crystal silicon located on a top surface of the buried oxide layer. Transistors and possibly other components of the integrated circuit may be formed in the SOI film. The thickness of the buried oxide layer may be limited so as to provide a desired level of performance of short channel metal oxide semiconductor (MOS) transistors in the SOI film. For example, attaining a desired level of off-state leakage current in the short channel MOS transistors may require the buried oxide layer to be no thicker than a certain maximum thickness.
The integrated circuit may include an extended drain MOS transistor with a drift region in the drain region adjacent to the channel region, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, a double-diffused metal oxide semiconductor (DMOS) transistor or a drain extended metal oxide semiconductor (DEMOS) transistor. It may be desired to operate the extended drain MOS transistor at a higher voltage than the breakdown voltage of the buried oxide layer. Previous attempts to integrate the extended drain MOS transistor have been problematic. One approach has been to increase the thickness of the SOI layer, which may undesirably increase the off-state leakage current in the short channel MOS transistors. Other approaches involve forming an aperture in the buried oxide layer to accommodate a p-n junction proximate to the aperture, which is reverse biased to deplete the handle wafer under the extended drain MOS transistor and thereby reduce the electric field across the buried oxide layer. Patterning the buried oxide layer to form the aperture prior to forming the SOI film may undesirably increase fabrication cost and complexity of the integrated circuit. Similarly, forming a patterned buried oxide layer by selectively ion implanting oxygen may undesirably degrade performance parameters of the integrated circuit as well as undesirably increase fabrication cost and complexity of the integrated circuit.